This disclosure relates generally to a method of modifying exposed surfaces of wafers suited for semiconductor fabrication and particularly to a method of modifying exposed surfaces of structured wafers suited for semiconductor fabrication using an abrasive article.
During integrated circuit manufacture, semiconductor wafers used in semiconductor fabrication typically undergo numerous processing steps, including deposition, patterning, and etching steps. Details of these manufacturing steps for semiconductor wafers are reported by Tonshoff et al., “Abrasive Machining of Silicon”, published in the Annals of the International Institution for Production Engineering Research, (Volume 39/2/1990), pp. 621-635. In each manufacturing step, it is often necessary or desirable to modify or refine an exposed surface of the wafer in order to prepare the wafer for subsequent fabrication or manufacturing steps.
For example, after a deposition step, the deposited material or layer on a wafer surface generally needs further processing before additional deposition or subsequent processing occurs. In another example, after an etching step, there is often a need to deposit either, or both, conducting or insulating materials in layers on the etched surface areas of a wafer. A specific example of this process is used in metal Damascene processes.
In the Damascene process, a pattern is etched into an oxide dielectric layer. After etching, optional adhesion/barrier layers are deposited over the entire surface and then a metal is deposited over or on top of the adhesion/barrier layers. The deposited metal layer is then modified, refined or finished by removing the deposited metal and regions of the adhesion/barrier layer on the surface. Typically, enough surface metal is removed so that the outer exposed surface of the wafer comprises both metal and an oxide dielectric material. A top view of the exposed wafer surface would reveal a substantially planar surface with metal corresponding to the etched pattern and dielectric material adjacent to the metal. The metal(s) and oxide dielectric material(s) located on the modified surface of the wafer inherently have different physical characteristics, such as different hardness values. An abrasive article used to modify a wafer produced by the Damascene process must be carefully designed so as to simultaneously modify the materials without scratching the surface of either material. Further, the abrasive article must be able to create a substantially planar outer exposed surface on a wafer having an exposed area of a metal and an exposed area of a dielectric material.
Such a process of modifying the deposited metal layer until the oxide dielectric material is exposed on the wafer outer surface leaves little margin for error because of the submicron dimensions of the metal features located on the wafer surface. It is clear that the removal rate of the deposited metal must be fast to minimize manufacturing costs. Further, metal removal from areas which were not etched must be complete. Still further, metal remaining in etched areas must be limited to discrete areas or zones. Yet further, the remaining metal must be continuous within an area or zone to ensure proper conductivity. In short, the metal modification process must be uniform, controlled, and reproducible on a submicron scale.
Furthermore, as a method for isolating elements of a semiconductor device, a great deal of attention has recently been directed towards a shallow trench isolation (STI) process where a silicon nitride layer is formed on a silicon substrate, shallow trenches are formed via etching or photolithography, and a dielectric layer is deposited to fill the trenches. Due to variation in the depth of trenches, or lines, formed in this manner, it is typically necessary to deposit an excess of dielectric material on top of the substrate to ensure complete filling of all trenches.
The excess dielectric material (e.g., an oxide) is then typically removed by a chemical-mechanical planarization process to expose the silicon nitride layer. In order to achieve a highly planar surface, the height of the nitride layer and the remaining trench oxide layer, should be substantially the same. Generally, past practice has been to emphasize selectivity for oxide polishing in preference to silicon nitride polishing. Thus, the silicon nitride layer has served as a stopping layer during the chemical-mechanical planarization process, as the overall polishing rate has decreased upon exposure of the silicon nitride layer.
Compositions and methods for planarizing or polishing the surface of a substrate are well known in the art. One conventional method of modifying or refining exposed surfaces of wafers employs methods that treat a wafer surface with a slurry containing a plurality of loose abrasive particles dispersed in a liquid. Typically this slurry is applied to a polishing pad and the wafer surface is then ground or moved against the pad in order to remove or take off material on the wafer surface. Generally, the slurry also contains agents which chemically react with the wafer surface. This type of process is commonly referred to as a chemical-mechanical planarization (CMP) process.
One problem with CMP slurries, however, is that the process must be carefully monitored in order to achieve a desired wafer surface topography. A second problem is the mess associated with loose abrasive slurries. Another problem is that the slurries generate a large number of particles which must be removed from the surface of the wafer and disposed of following wafer treatment. Handling and disposal of these slurries generates additional processing costs for the semiconductor wafer fabricator.
An alternative to CMP slurry methods uses an abrasive article to modify or refine a semiconductor surface. This alternative CMP process is reported in International Publication No. WO 97/11484, published Mar. 27, 1997. The reported abrasive article has a textured abrasive surface which includes abrasive particles dispersed in a binder. In use, the abrasive article is contacted with a semiconductor wafer surface, often in the presence of a fluid or liquid, with a motion adapted to modify a single layer of material on the wafer and provide a substantially planar, uniform wafer surface. Use of an abrasive article overcomes a significant number of problems associated with CMP slurries.
Embodiments of the present disclosure exploit the advantages afforded by use of abrasive articles to modify surfaces of semiconductor wafers in order to expose at least two different materials, typically having different hardness values on the surface of a wafer.